Liquid-crystal display top gate thin film transistor with particular connection between the drain and the display electrode

ABSTRACT

The present invention relates to a thinfilm transistor array designed to drive an active-matrix type liquid-crystal panel to be incorporated in a liquid-crystal display device, and is to offer a thinfilm transistor array solving the conventional problems of disconnections possible between the display electrodes and the drain electrodes and short-circuits possible between the display electrodes and the data wiring. By these, high-quality images can be displayed with a high reliability can be obtained together with an improved fabrication process thereof. In order to accomplish these objectives of the invention, the display electrodes of said thinfilm transistor array are disposed between the gate insulation layer and the inter-insulation layer, and the display electrodes are connected to the drain electrodes by means of a data wiring disposed through contact holes provided through the inter-insulation layer. Furthermore, the possibility of short-circuits can be minimized by insulating and isolating the display electrodes from the data wiring by means of inter-insulation layers, so that the distance between the data wiring and the display electrode can minimized and a remarkable improvement of the displayed image quality can be obtained.

FIELD OF THE INVENTION

This invention relates to a thinfilm transistor array comprised ofswitching elements and display electrodes provided to drive aliquid-crystal display panel to be incorporated in a display device, itsfabrication process thereof, and a liquid-crystal display deviceutilizing the same.

BACKGROUND OF THE INVENTION

A conventional fabrication process of a thinfllm transistor array is nowexplained below by taking an example for a case where it is used tofabricate a liquid-crystal display device.

FIG. 7 shows a fabrication process of top-gate type polysilicon thinfilmtransistor array to be incorporated in an active matrix typeliquid-crystal display device. As shown in FIG. 7(a), polysiliconthinfilm 14 is disposed on transparent substrate 11 first, and saidpolysilicon thinfilm 14 is formed into a thinfilm transistor array.

After disposing gate-insulation layer 15 of a silicon-oxide thinfilm onpolysilicon thinfilm 14, gate electrode 16 is formed on gate-insulationlayer 15. A phosphor dopant is then implanted in source and drainregions of thinfilm transistor array by using an ion-implantation methodwherein said dopant is implanted into polysilicon thinfilm 14 throughgate-insulation layer 15 by using gate electrodes 16 as a mask. Afterapplying a process to activate said implanted dopant, silicon-oxideinter-insulation layer 17 is then formed as shown in FIG. 7(b).

After this, contact holes 20 are provided in gate insulation layer 15and inter-insulation layer 17 formed on said source and drain regions ofthinfilm transistor, and, as shown in FIG. 7(c), display electrodes 12made of ITO (Indium Tin Oxide) are disposed on these. The fabricationprocess of thinfilm transistor array is completed then by depositingdata wiring 18 on these.

Succeeding to the above, problems associated with the conventionalfabrication process of thinfilm transistor array shown in FIG. 7 are nowexplained in the following.

The first problem is a high probability of disconnections of displayelectrodes 12.

FIG. 8 shows an enlargement of region-A of contact hole 20 shown in FIG.7(c), indicating an edge step of which height corresponds to the sum ofthe thicknesses of gate insulation layer 15 and inter-insulation layer17.

As shown in FIG. 8, since the height of step of contact hole is 500 nm(sum of 100 nm of gate insulation layer and 400 nm of inter-insulationlayer) while the thickness of ITO layer of display electrode 12 is 100nm, the step coverage of ITO layer at the contact hole step isinadequate, increasing the probabilities of disconnections and othertroubles.

In preventing the disconnections of display electrodes 12 at contactholes, the inadequate step coverage had been corrected by providing atapered cross-section of gate insulation layer 15 and inter-insulationlayer 17 obtained by applying a controlled etching process in formingcontact holes 20.

The second problem relates to short-circuits between the displayelectrode 12 and the data wiring 18.

FIG. 9 shows a top view of thinfilm transistor array designed to beincorporated in a liquid-crystal display device shown in FIG. 7. Thiscross-section at A-A' line shown in FIG. 9 corresponds to the one shownin FIG. 7(c).

As seen from the data wiring 18 and display electrode 12 disposed at aclose distance shown by B-B' line in FIG. 9 and the cross-section ofthese components at B-B' line in FIG. 4(a), no insulation layer had beenprovided between the data wiring 18 and the display electrode 12 ofconventional thinfilm transistor array.

Therefore, the probability of short-circuits between the data wiring 18and the display electrode 12 due to foreign particles introducedthere-between during the patterning process of these should had beenfairly high.

Since the probability of such short-circuits is higher for the shorterdistance between the data wiring 18 and the display electrode 12, aproper distance had to be provided in order to reduce the probability ofsuch, sacrificing the display area as a result of this.

The third problem relates to corrosion of said circuit componentspossible during the patterning process of these.

During the patterning process of data wiring 18 made of an aluminumlayer, corrosion of the aluminum layer may take place during thephotolithographic process employing a positive type photoresist sincethe aluminum layer and the ITO layer of display electrode 12 aredisposed on a common plane.

Thus, a negative type photoresist had to be employed particularly duringthe patterning process of data wiring 18. As for the corrosion processof Al-ITO layer possible during said photolithographic process, thedetails of it are explained in Japanese Patent ApplicationHei-5-1111439.

SUMMARY OF THE INVENTION

One of the objects of the present invention is to offer a thinfilmtransistor array of higher reliabilities together with a new fabricationprocess of higher production yield solving the problems including theshort-circuits between the data wiring and the display electrode.Moreover, the present invention is to offer a new liquid-crystal displaydevice of higher aperture, yielding an improved display image qualityattained by employing the invented thinfilm transistor array.

In order to attain these objectives, the invented top gate type thinfilmtransistor array of which semiconductor active layer is made of apolysilicon thinfilm, is provided with display electrodes disposedbetween the gate insulation layer and the inter-insulation layer, andsaid display electrodes are connected to the drains of thinfilmtransistors through data wiring disposed through contact holes providedon said inter-insulation layer.

Moreover, the display electrodes of the present invention are disposedbetween the first inter-insulation layer disposed on said gateinsulation layer and gate electrodes and said second inter-insulationlayer disposed above the first inter-insulation layer, and said displayelectrodes are connected to the drains of thinfilm transistors throughthe gate insulation layer disposed on the drain regions of thinfilmtransistors and the data wiring connecting the contact holes provided inthe first and the second inter-insulation layers.

Furthermore, the fabrication process of the present invention consistsof a process to deposit a polysilicon thinfilm on a transparentsubstrate and to fabricate said thinfilm into a desired transistorpattern, a process to deposit a gate insulation layer cover saidpolysilicon thinfllm, a process to deposit gate electrodes on said gateinsulation layer, a process to form source and drain regions of thinfilmtransistors by implanting a dopant into said polysilicon thinfilm usingsaid gate electrodes as a mask, a process to form display electrodesmade of conductive oxide thinfilm on said gate insulation layer, aprocess to deposit an inter-insulation layer on said display electrodes,a process to form contact holes on each of the inter-insulation layerdeposited on said source and drain regions of thinfilm transistor, andspecified parts of said inter-insulator layer of said displayelectrodes, and a last process to deposit a protection layer on at leastthe entire surface of thinfilm transistors disposed within the thinfilmtransistor array.

Moreover, in the invented fabrication processes, at least a siliconoxide layer or a silicon nitride layer is used as an inter-insulationlayer, and at least a silicon nitride layer is used as a protectionlayer disposed on the entire surface of said thinfilm transistor for asa protection layer disposed on the surface of said display electrode.

Furthermore, the fabrication process of the present invention consistsof a process to fabricate a polysilicon thinfilm on a transparentsubstrate and to fabricate said thinfilm into a desired form oftransistor, a process to deposit a gate insulation layer covering saidpolysilicon thinfilm, a process to deposit gate electrodes on said gateinsulation layer, a process to implant a dopant into said polysiliconthinfilm using said gate electrodes as a mask in order to form sourceand drain regions of thinfilm transistors, a process to deposit a firstinter-insulation layer covering said gate electrodes, a process todeposit display electrodes made of conductive oxide on said firstinter-insulation layer, a process to deposit a second Inter-insulationlayer covering said display electrodes, a process to form contact holeson specified parts of said second inter-insulation layer deposited onsaid display electrode, and through said gate inter-insulation layer,the first inter-insulation layer, and second inter-insulation layerdeposited on said source and drain regions of thinfilm transistors, aprocess to deposit a data wiring on said source and drain regions ofthinfilm transistors, and a last process to deposit a protection layeron at least the entire surface of thinfilm transistors disposed withinthe thinfilm transistor array.

Moreover, in the invented fabrication process, at least a silicon oxidelayer or silicon nitride layer is used as said first and secondinter-insulation layers, and at least a silicon nitride layer is used asa protection layer deposited on the entire surface of said thinfilmtransistors or as a protection layer deposited on the surface of saiddisplay electrodes.

Furthermore, the present invention offers a liquid-crystal displaydevice comprised of a pair of transparent substrates filled with liquidcrystal and a thinfilm transistor array of the invention deposited onone of said transparent substrates by which said liquid crystal elementsare switched through said display electrodes of said thinfilm transistorarray displaying images and characters on said liquid-crystal displaydevice.

Therefore, according to the construction of the invented thinfilmtransistor array, the disconnections and other failures possible at thejunctions between the display electrodes (made of a conductive oxidelayer) and the thinfilm transistors can be effectively prevented, andthe possibilities of short-circuits (appeared as defective images) dueto foreign particles introduced during its fabrication processes canalso be largely reduced because the display electrodes and the datawiring of thinfilm transistors are insulated and isolated by, said firstinter-insulation layer.

Thus, it is possible to employ a shorter distance between the datawiring and the display electrodes of thinfilm transistor than that ofconventional thinfilm transistor, so that the aperture of display areaof thinfilm transistor array can be considerably increased, and theseare highly effective to improve the quality of displayed images.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(a), 1(b ), and 1(c) show a construction of the thinfilmtransistor which is a first embodiment of the invention, andcross-sections of its fabrication processes.

FIGS. 2(a), 2(b), and 2(c) show a construction of the thinfilmtransistor which is a second embodiment of the invention, andcross-sections of its fabrication processes.

FIG. 3 shows a partial planar view of an invented thinfilm transistorarray showing its structure when it is incorporated in a liquid crystaldevice.

FIGS. 4(a), 4(b), and 4(c)show a cross-section of thinfilm transistorarray sectioned along B--B' line shown in FIGS. 3 and 9.

FIG. 4(a) shows a construction of conventional thinfilm transistor arrayshown in FIG. 7(c), FIG. 4(b) shows a construction of thinfilmtransistor array which is the first embodiment of the invention shown inFIG. 1(c), and FIG. 4(c) shows a construction of thinfilm transistorarray which is the second embodiment of the invention shown in FIG.2(c).

FIG. 5 is a cross-section of thinfilm transistor array sectioned alongthe C--C' line shown in FIGS. 3 and 9. FIG. 5(a) shows a construction ofconventional thinfilm transistor array shown in FIG. 7(c), FIG. 5(b)shows a construction of thinfilm transistor array which is the firstembodiment of the invention shown in FIG. 1(c), and FIG. 5(c) shows aconstruction of thinfilm transistor array which is the second embodimentof the invention shown in FIG. 2(c).

FIG. 6 is a cross-section of liquid-crystal display device using aninvented thinfilm transistor array showing its construction.

FIGS. 7(a), 7(b), and 7(c) show a cross section of a conventionalthinfilm transistor array during its fabrication;

FIG. 8 is an enlargement of region-A shown in FIG. 7(c).

FIG. 9 is a partial planar view of conventional thinfilm transistorarray showing its construction.

DESCRIPTION OF PREFERRED EMBODIMENTS

An embodiment of the present invention is now explained below by takingan example for fabrication processes of a thinfilm transistor array tobe incorporated in an active matrix type liquid-crystal display device.In the below-shown description of this embodiment of the invention, theelectrode of thinfilm transistor at the display electrode side isdefined as a drain electrode.

EMBODIMENT-1

FIG. 1 shows cross-sectional fabrication processes of thinfilmtransistor array which is a first embodiment of the invention.

As shown in FIG. 1(a), polysilicon thinfilm 14 is deposited first ontransparent substrate 11 of such as glass for a thickness of 100 nm. Thedeposition of polysilicon thinfilm is started with a deposition ofamorphous silicon thinfilm using a plasma CVD device in which silane(SiH₄) gas and hydrogen (H₂) gas are introduced. Tile hydrogenconcentration within the amorphous silicon thinfilm is then reduced byapplying a heat-treatment in a nitrogen atmosphere kept at a temperatureof 450° C. for a period of 120 minutes. By applying a irradiation ofXeCl excimer laser (of a wavelength of 308 nm) onto the amorphoussilicon thinfilm, said amorphous silicon thinfilm is transformed intopolysilicon thinfilm 14.

By applying a patterning process, said polysilicon thinfilm 14 is madeinto a form of thinfilm transistor, and after this, gate insulationlayer 15 of silicon oxide is deposited on said polysilicon thinfilm 14for a thickness of 100 nm.

Gate electrodes 16 are then formed by depositing a tantalum (Ta)thinfilm for a thickness of 200 nm first on said gate insulation layer15 and by removing an excess part of said tantalum thinfilm by means ofchemical etching. Then, by implanting a phosphor ion into polysiliconthinfilm 14 through gate insulation layer 15 by using said gateelectrodes 16 as a mask in order to form the source and drain regions ofthinfilm transistor The phosphor-ion implantation is conducted under acondition employing an accelerating voltage of 80 kV in order to attaina total implantation concentration of 1×10¹⁵ cm². After this, theimplanted dopant is activated by applying a heat-treatment in a nitrogenatmosphere kept at a temperature of 600° C. for a period of 24 hours.

As shown in FIG. 1(b), a layer of display electrode 12 of a conductiveoxide layer (ITO layer) is then deposited on gate insulation layer 15for a thickness of 100 nm. After depositing inter-insulation layer 17 ofa silicon oxide thinfilm on the entire surface of thinfilm transistorsand display electrodes 12 for a thickness of 400 mm, the substrate issubjected to a hydrogen plasma treatment in order to terminate thedangling bonds existing in polysilicon thinfilm 14 at a highconcentration.

Said hydrogen plasma treatment is performed by using a parallel platetype plasma CVD device under a condition of hydrogen gas pressure of 1Torr, RF power of 300 W, substrate temperature of 300° C. and atreatment period of 2 hours. After the hydrogen plasma treatment,contact holes are provided in the gate insulation layer 15 andinter-insulation layer 17 as shown in FIG. 1(c).

Then, electrical connections to each of the source and drain regions andthe display electrodes are made by depositing data wiring 18 of analuminum thinfilm for a thickness of 700 nm, and the fabricationprocesses of said thinfilm transistor array constituting the displaypixels are completed by a deposition of protection layer 21 of siliconnitride on at least the entire surface of thinfilm transistors for athickness of 500 nm. In addition to this, it is possible to provideprotection layer 21 on the surface of display electrode 12 when a changeof display characteristics of liquid crystal display device is desired.

EMBODIMENT-2

FIG. 2 shows stepwise cross-sectional fabrication processes of thinfilmtransistor array in a second embodiment of the invention.

As shown FIG. 2(a), polysilicon thinfilm 14 is deposited first ontransparent substrate 11 for a thickness of 100 nm. For this, anamorphous silicon thinfilm is deposited by using a low-pressure CVDdevice in which silane (SiH₄) and hydrogen (H₂) gases are introducedsetting the substrate temperature at 550° C.

Said amorphous silicon thinfllm is then crystallized into polysiliconthinfilm 14 by applying a heat-treatment in a nitrogen atmospherekeeping the substrate temperature at 600° C. for a period of 10 hours.

After applying a patterning process to transform said polysiliconthinfilm 14 into a form of thinfilm transistor, gate insulation layer 15of silicon oxide is deposited on polysilicon thinfilm 14 for a thicknessof 100 nm.

Gate electrodes 16 are then formed by depositing a tantalum (Ta)thinfilm for a thickness of 200 nm on gate-insulation layer 15 and byremoving an excess part of said tantalum thinfilm by means of chemicaletching. Then, by implanting a phosphor dopant into the polysiliconthinfilm 14 through gate-insulation layer 15 by using said gateelectrodes 16 as a mask to form source and drain regions of thinfilmtransistor.

The phosphor-ion implantation is conducted under a condition of anaccelerating voltage of 80 kV to obtain a total concentration of 1×10¹⁵cm². After this, the implanted dopant is activated by applying aheat-treatment in a nitrogen atmosphere kept at a temperature of 600° C.for a period of 24 hours.

As shown in FIG. 2(b), display electrode 12 made of a conductive oxidethinfilm (ITO film) is deposited on a first inter-insulation film 17a ofsilicon oxide for a thickness of 300 nm. Then, a second inter-insulationlayer 17b of silicon oxide is deposited for a thickness of 100 nm. Afterthis, the substrate is subjected to a hydrogen plasma treatment in orderto terminate the dangling bonds existed abundantly In polysiliconthinfilm 14.

Said hydrogen plasma treatment is performed by using a parallel platetype plasma CVD device under a condition of hydrogen gas pressure of 1Torr, RF power of 300 W, substrate temperature of 300° C. and atreatment period of 2 hours. After said hydrogen plasma treatment,contact holes are provided in gate insulation layer 15 and the first andthe second inter-insulation layers 17a and 17b as shown in FIG. 2(c).

Then, electrical connections to each of the source and drain regions andto the display electrodes are made by depositing data wiring 18 ofaluminum thinfilm for a thickness of 700 nm, and the fabrication processof thinfilm transistor array consisted of display pixels is completed bydepositing protection layer 21 made of silicon nitride at least on theentire surface of thinfilm transistor array for a thickness of 500 nm.In addition to this, it is possible to deposit protection layer 21 onthe surface of display electrode 12 when a change of displaycharacteristics of liquid-crystal display device is desired.

Although the first and the second silicon-oxide inter-insulation layers17a and 17b are employed in this second embodiment of the invention, thesame effect can be obtained by using a thinfilm other than the siliconoxide thinfilm such as a silicon nitride thinfilm or a laminatedthinfilm consisted of a silicon oxide thinfilm and a silicon nitridethinfilm.

As shown in the first and the second embodiments of the invention, thedrain regions which had been directly connected to the displayelectrodes can now be connected through data wiring 18 when the inventedfabrication method is employed. Thus, a substantial reduction of contactfailures or disconnections can be realized together with a substantialimprovement of production yield of thinfilm transistor array.

FIG. 3 shows a top view of liquid-crystal display device are employingthe invented thinfilm transistor array, and FIG. 4 is a cross-sectionalconstruction of it showing the relative positions of data wiring 18 anddisplay electrodes 12 along the B--B' line of FIGS. 3 and 9.

Since the display electrodes 12 and data wiring 18 had been coplanarlydisposed in the conventional case as shown In FIG. 4(a), a properdistance d had to be provided between the display electrode 12 and thedata wiring 18 in order to reduce the short-circuits possiblethere-between.

In contrast to the conventional case shown in the above,inter-insulation layer 17 is disposed between the display electrode 12and data wiring 18 of the invented thinfilm transistor array as shown inFIGS. 4(b) and 4(c). Since these two components can be insulated andisolated each other completely, the electrical shortage between adisplay electrode and a data wiring due to dusts introduced during thefabrication process can be largely reduced and the production yield ofthinfilm transistor array can be improved substantially. PG,14

FIG. 5 shows a cross-section at C--C' line specified in FIGS. 3 and 9showing relative positions of gate electrode 16 and display electrode 12of thinfilm transistor array. As shown in the second embodiment of theinvention, since the first inter-insulation layer 17a is providedbetween the gate electrode 16 and the display electrode 12, these twocomponents are insulated and isolated each other. Thus, the electricalshortage between a display electrode and a data wiring due to dustsIntroduced during its fabrication process can be reduced and theproduction yield of thinfilm transistor array can be improvedsubstantially also.

Moreover, since the probability of short-circuits can be reduced to areasonably low level by employing the invented fabrication process, thedistance d between the data wiring 18 and the display electrode 12 canbe designed at its minimum, improving the display area aperture ofliquid-crystal display device and the contrast thereof also. Moreover,since data wiring 18 and display electrode 12 are insulated and isolatedeach other by means of inter-insulation layer, the possible erosion ofaluminum wiring during the photolithographic process forming data wiring18 can be eliminated.

EMBODIMENT-3

FIG. 6 shows a cross-section of unit pixel of liquid-crystal displaydevice in which the invented thinfilm transistor array is incorporated.The liquid-crystal layer is sandwiched between two transparent glasssubstrates 11 constituting display cells.

In the cell, color filter layer 22 and black matrix 23 are disposed onthe surface of one of the substrates and counter electrode 25 made ofITO thinfilm is deposited on over-coat layer 24, while a thinfilmtransistor array is integrally disposed on the surface of the othersubstrate by using fabrication processes explained in Embodiment-1 or -2of the invention. The protection layer on the display electrode isomitted in this case. Since the thinfilm transistor array is made of apolysilicon layer, the peripheral circuits driving the thinfilmtransistor array can be constituted of polysilicon thinfilm transistors,and these are disposed at an outer rim of said transparent substrate 11.

As depicted in FIG. 6, a major portion of the protection layer, formedover the thinfilm transistor array, is omitted to expose the displayelectrode. The elimination of this portion of the protection layerachieves some clear advantages over the prior art. First, theelimination decreases the resistivity due to the protection layer, whichon a transparent substrate and to fabricate said thinfilm.

What is claimed is:
 1. A liquid-crystal display device comprised ofdisplay cells the device consisting of a pair of transparent substratesfilled with liquid-crystal and a top-gate type thinfilm transistor arraydisposed on one of said transparent substrate, wherein images and/orcharacters can be displayed on said display cells by switching saidliquid crystal by controlling display electrodes of said thinfilmtransistor array,said display electrodes being disposed between a firstinsulation layer which is disposed on gate electrodes which are disposedon a gate insulation layer and a second insulation layer disposed onsaid first insulation layer, said display electrodes being connected todrain regions of said thinfilm transistors with a data wiring through acontact hole disposed in said second insulation layer and through acontact hole disposed in said gate insulation layer, said firstinsulation layer and said second insulation layer formed on an upperside of said drain regions, and a protection layer being formed on saidthinfilm transistor array, wherein a major part of said protection layeron said display electrode is omitted to expose said display electrode.